4. (a) Analyze the circuit shown in Figure 3 below, and draw the state diagram for the circuit. Show all the steps in deriving the state diagram. CLK- 3(b) D D Q Q. Figure 3 (10 Marks) The data on propagation delays of the components used in part (a) are summarized in Table 4. Determine the maximum frequency of operation for the circuit with setup time margin of 5 ns. Table 4 Component tplh(ns) tphi(ns) tsu(ns) D flip-flop 8 10 5 XOR 6 4 4 3 (5 Marks) AND (c) For the circuit in part (a), implement a functionally equivalent circuit using only 3 flip-flops. You are free to choose any type of flip-flops deemed appropriate for the purpose. Note: Question No. 4 continues on page 5. (5 Marks)