You Answered Correct Answer A synchronous read cycle of a 9.4-MHz bus has 12 wait states and no block transfer cycle. How long does it take to read 63 kB of data if the bus is 64 bits wide and there is 2 clock cycle\[s] before and 1 clock cycle\[s] after the wait state\[s]? (Give your answer in ms to three decimal places.) 12.01 12.868 margin of error +/- 0.001