A: Design a sequential circuit with two T flip-flops A and B and two inputs E and F. If E = 0, the circuit remains in the same state regardless of the value of F. When E = 1 and F = 0, the circuit goes through the state transitions from 00 to 10, to 01, to 11, back to 00, and repeats. When E = 1 and F = 1, the circuit goes through the state transitions from 00 to 11, to 10, to 01, back to 00, and repeats. (25 mark) B: For the resulted design in A. how many configurable logic block (CLB) you would need to implement your design in the FPGA if the CLB structure is as follows, then program the CLBs: (15 mark) Lock-Up Table (LUT)