11. For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache. (1 word = 64-bits) [55] Tag 63-10 Index 9-5 (a) What is the cache block size (in words)? [5] (b) How may blocks does the cache have? [5] Offset 4-0 (c) What is the ratio between total bits required for such a cache implementation over the data storage bits? Let us assume each cache block includes 1-bit "valid" field. [10] Beginning from power on, the following byte-addressed cache references are recorded. 0x000, 0x004, 0x010, 0x084, 0x0E8, 0x00, 0x400, 0x01E, 0x08c, exc1c, 0x084, 0x884 (d) For each reference, complete the following table. "Replace" represents which bytes replaced if any. [20] Address 0х000 0x004 0x010 0x084 0x0E8 0x0A0 0x400 0x01E 0x08C 0xC1C 0x0B4 0x884 Tag Index Offset Hit/Miss Replace (e) What is the hit ratio? [5] (f) List the final state of the cache, with each valid entry represented as a record of <index, tag, data>. For example, [10] <0, 3, Mem[0xc00]-Mem[0xC1F]>