The figure shown below is a 3-input NAND gate with pre-charge and evaluation stages shown. What are the problems associated with evaluation stage with input status being 110 combination. Explain the problem and possible solution to fix the problem. +VDD Mp ON VDD Mp A₁ =0 Cout A2° A3 + out → VDD 1 0 Yout Yout→Vf =0° C3V3 Mn = 1 CV3=0v Mn (a) Precharge network (b) Charge sharing circuit Note use the following equation to explain the charge sharing issues. Q = CoutV+CV+C₂Vƒ