Problem 1 [30 pts] Design a Verilog code for '101' sequence detection module with various modeling styles: (i) behavioral Verilog description with state table; (ii) a data flow Verilog description with logic equations; and (iii) a structural Verilog description. State table and structural implementation are given below. Submit your codes and test results with waveform for (i)(ii) and (iii). Clock should have a period of 20ns. For the flip-flop, either rising-edge triggering or falling-edge triggering will be OK. X = Z 0 01 1 0 1 1 0 0 1 = 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 010 100 Present Next State Present Output State X=0 X=1 X=0 X=1 So So S₁ 0 0 Clock S₁ S2 S₁ 0 0 S₂ So S₁₁ 0 1 A A B' B CK CK D Z