ww Vcc +12 V R₁ • 22 ΚΩ Rc 470 Ω R 4.7 ΚΩ RE 130 Ω Figure 6 30) Refer to Figure 6. Assume Vc -0.07 V and VB = 0.7 V. The fault may be that A) RC is open C) VCC has dropped to 8 V B) RE is open D) VCC is open 30) 31) D) R₁ is open 32) 31) Refer to Figure 6. Assume you find VC 12 V and VB 0.08 V. The fault may be that A) R2 is open B) RE is open C) RC is open 32) Refer to Figure 6. Assume you find VC 12 V and VB-2 V. The fault may be A) that RC is open C) either A or B could account for this B) that the transistor base is open D) none of the above 33) D) VTH-2.1 V 34) D) RTH = 4.7 k 35) 33) Refer to Figure 6. If you Thevenize the input to the base, the Thevenin voltage is A) VTH = 3.5 V B) VTH = 0.7 V C) VTH - 2.6 V 34) Refer to Figure 6. If you Thevenize the input to the base, the Thevenin resistance is A) RTH = 22 k B) RTH = 26.7 k 35) A stiff voltage divider is one in which C) RTH = 3.9 kc A) the Q-point will be centered C) loading effects can be ignored B) has very large bias resistors D) two voltage sources are used 36) 36) Of the methods shown below, the one that has the most stability is A) emitter feedback bias C) base bias B) emitter bias D) collector feedback bias 7