Assume the following: ⚫. The memory is byte addressable. ⚫. Memory accesses are to 1-byte words (not to 4-byte words). • . Addresses are 7 bits wide. . . The cache is 4-way associative cache (E=4), with a 2-byte block size (B-2) and 4 sets (S=4). • The cache contents are as shown below Set #Way #0 Way #1 Way #2 Way #3 V=1;Tag=0x2; Data = V=1;Tag=0x5; Data =V=1;Tag=0x1; Data = V=1;Tag=0x0; Data = 0: 0x08 0x74 0xd5 0x32 Ox4e Oxea Oxef 0x12 V=1;Tag=0x5; Data = V=1;Tag=0x1; Data =V=1;Tag=0x4; Data = V=1;Tag=0x6; Data = 1: 0x46 Oxda 0x2f 0x17 Oxb2 Oxa8 0x56 0x5f 2: Ox13 0x5a V=1;Tag=0x3; Data = V=1;Tag=0x0; Data = V=1;Tag=0xb; Data = V=1;Tag=0x5; Data = Ox32 0xd3 0xc5 0x0a 0x30 Oxeb V=1;Tag=0x5; Data = V=1;Tag=0x2; Data = V=1;Tag=0x4; Data = V=1;Tag=0xe; Data = 3: Ox38 0x8b Oxde 0x37 0x89 0xb1 Ox3e 0x38 Assume that memory address 0x28 has been referenced by a load instruction. Indicate the cache entry accessed and the cache byte value returned in hex. Indicate whether a cache miss occurs. If there is a cache miss, enter "-" for the "Cache Byte Returned". For values that need a hexidecimal value, do not enter leading zeros even if leading zeros are shown in the value above. Cache block Offset (CO) Ox × Cache set index (CI) Ox Cache tag (CT) Ox × Cache hit (Y/N)? х Cache byte returned Ox x