2. Design B: Implement a 4-bit ripple carry adder/subtractor using structural VHDL. The circuit will have two 4-bit data inputs (A and B), a control line Add/Sub, a 4- bit data outputs (S) and a carry out bit (Cout). Devise a set of test input vectors (values) that will be used to verify that the circuit is working properly. You need two VHDL files (fulladd.vhd) and (adder16b.vhd) to implement the design. fulladd.vhd will implement a single-bit full adder. Adder4b.vhd will create four instances of the single-bit full adder. Four XOR gates will be needed to create the hybrid adder/subtractor.