3.18 [20] <$3.4> Using a table similar to that shown in Figure 3.10, calculate 74 divided by 21 using the hardware described in Figure 3.8. You should show the contents of each register on each step. Assume both inputs are unsigned 6-bit integers. 64-bit ALU Divisor Shift right 64 bits Remainder 64 bits Write Control test Quotient Shift left 32 bits FIGURE 3.8 First version of the division hardware. The Divisor register, ALU, and Remainder register are all 64 bits wide, with only the Quotient register being 32 bits. The 32-bit divisor starts in the left half of the Divisor register and is shifted right I bit each iteration. The remainder is initialized with the dividend. Control decides when to shift the Divisor and Quotient registers and when to write the new value into the Remainder register. Iteration Stop Quotient Divisor Remainder 0 Initial values 0000 0010 0000 0000 0111 1: Rem Rem- Div 0000 0010 0000 1 2b: Rem <0+Div, sill Q, Q0=0 0000 0010 0000 110 0111 0000 0111 3: Shift Div right 0000 0001 0000 0000 0111 1: Rem Rem - Div 0000 0001 0000 2 2b: Rem 0+Div, sll Q. Q0=0 0000 0001 0000 3: Shift Div right 0000 0000 1000 111 0111 0000 0111 0000 0111 1: Rem Rem-Div 0000 0000 1000 3 2b: Rem 0+Div, sll Q, Q0=0 0000 0000 1000 111 1111 0000 0111 3: Shift Div right 0000 0000 0100 0000 0111 1: Rem Rem - Div 0000 0000 0100 0000 0011 4 2a: Rem 20sll Q, Q0-1 0001 0000 0100 0000 0011 3: Shift Div right 0001 0000 0010 0000 0011 1: Rem Rem-Div 0001 0000 0010 000 0001 5 2a: Rem 20 sll Q, Q0-1 0011 0000 0010 0000 0001 3: Shift Div right 0011 0000 0001 0000 0001 FIGURE 3.10 Division example using the algorithm in Figure 3.9. The bit examined to determine the next step is circled in color.