Digital logic 14.18 Digital lock, I. Draw a state diagram and a state table for a digital lock. The lock has two inputs a and b and one output, unlock. The output is asserted only if the sequence a, b, a, a is observed. Each element of the sequence must last for one or more cycles, and there must be one or more cycles of both inputs low between the sequence elements. After unlocking, either input going high causes unlock to go low. 14.19 Digital lock, II. Implement, in Verilog, your digital lock state machine from Exer- cise 14.18.