Exercise 6.5: Shift Register with Load Figure 6.16 depicts a 4 × 1 (four stages of one bit each) shift register with data-load capa- bility (Pedroni 2008). When load = '0', it operates as a regular shift register. However, if load = '1', din is loaded into the DFFs at the next positive clock transition (thus the initial state of the flip-flops can be programmed). Design this circuit using VHDL. din(0) d. clk load Figure 6.16 din(1) d 9 d din(2) din(3) d प d q-dout Jo