5.3 For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag Index Offset 31-10 9-5 4-0 5.3.1 [5] <COD §5.3> What is the cache block size (in words)? 5.3.2 [5] <COD §5.3> How many entries does the cache have? 5.3.3 [5] <COD §5.3> What is the ratio between total bits required for such a cache implementation over the data storage bits? Starting from power on, the following byte-addressed cache references are recorded. Address 0 4 16 132 232 160 1024 30 140 3100 180 2180 5.3.4 [10] <COD §5.3> How many blocks are replaced? 5.3.5 [10] <COD §5.3> What is the hit ratio? 5.3.6 [10] <COD §5.3> List the final state of the cache, with each valid entry represented as a record of <index, tag, data>.