Exercise 5: A CPU produces the following sequence of read addresses in hexadecimal: 50, 104, 112, 68, OC, 34, 188, 68, 50, 54, 20, 34, 112, 5C, 14, 30. (15 points) Supposing that the 8-words cache is empty to begin with, and assuming an LRU replacement, determine whether each 10-bit address produces a hit or a miss for each of the following caches: (a) Direct mapped (b) Fully associative, and (c) Two-way set associative 50 104 112 68 81 34 188 68 50 54 20 34 112 5C 14 50 Direct Mapped Fully Associative 2-Way