Consider the following closed-loop system. 1 G₁(s) s(s+2) The desired closed-loop system performance specs are OS% ≤5% under step input, and the steady state error ≤0.2 under unit ramp input. a. Design a P controller and see whether it is possible to satisfy both performance specs. Provide a sketch of the root locus. b. If not, what type of controller should be designed? Choose between a phase lead compensator and a phase lag compensator and design it.