6.2 Include a synchronous clear input to the register of Fig. 6.2. The modified register will have a parallel load capability and a synchronous clear capability. The register is cleared syn- chronously when the clock goes through a positive transition and the clear input is equal to 1. (HDL-see Problem 6.35(a), (b).) apter 6 Registers and Counters Load 10 13 Clock FIGURE 6.2 Four-bit register with parallel load D D D C A₁ A D C A D C