Design a Mealy FSM to detect the sequence [1010] from the input sequence, x, where overlapping sequences are allowed. The output, z, is initially zero and switches to a 1 as soon as the trailing 0 bit is detected in the input sequence. The output then returns to 0 on the next clock cycle and remains there until the next [1010] sequence is detected. See below for an example input and output sequence. Use state names: S0, S1, S2, etc. where S0 in the initial state. Design with a minimum number of states. Create the Mealy FSM state diagram with the transitional arrows between states labeled with their input/output. Write the corresponding state/output table. X 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 N 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0