Exercise 7.3 Modify the single-cycle MIPS processor to implement one of the following instructions. See Appendix B for a definition of the instructions. Mark up a copy of Figure 7.11 to indicate the changes to the datapath. Name any new control signals. Mark up a copy of Table 7.8 to show the changes to the main decoder. Describe any other changes that are required. (a) s11 (b) lui (c) slti (d) blez Table 7.8 Main decoder truth table to mark up with changes Instruction Opcode Reg Write RegDst ALUSrc Branch MemWrite MemtoReg ALUOP R-type 000000 1 1 00 0 โพ 100011 1 0 1 0 1 SW 101011 0 X 1 0 1 X beq 000100 0 X 0 1 0 X 2885 10 00 00 01 Exercise 7.4 Repeat Exercise 7.3 for the following MIPS instructions. (a) jal (b) 1h (c) jr (d) srl Exercise 7.3 Modify the single-cycle MIPS processor to implement one of the following instructions. See Appendix B for a definition of the instructions. Mark up a copy of Figure 7.11 to indicate the changes to the datapath. Name any new control signals. Mark up a copy of Table 7.8 to show the changes to the main decoder. Describe any other changes that are required. (a) s11 (b) luf (c) siti (d) blez. Table 7.8 Main decoder truth table to mark up with changes Instruction Opcode Reg Write RegDst ALUSrc Branch MemWrite MemtoReg ALUOP R-type 000000 1 1 0 0 0 0 10 ไม่ 100011 1 0 1 0 0 1 00 SW 101011 0 X 1 0 1 X 00 beq 000100 0 X 0 1 0 X 01 Exercise 7.4 Repeat Exercise 7.3 for the following MIPS instructions. (a) jal (b) 1h (c) jr (d) srl