1. (20 points) Design a mod-7 counter. A mod-7 counter updates its output per clock rising edge according to the following sequence: 000, 001, 010, 011, 100, 101, 110, (then repeat the pattern....). en is enable control, resetn is reset control. Complete the following Verilog code: module mod7(clock, resetn, en, z); endmodule en z[2:0] clock resetn