Question - 1: Assume you are required to design a logic circuit enclosed in a black box to detect a password, which can be changed by an authorized administrator any time. The password is composed of a squence of a 4-bit decimal number, i.e., each bit is in the range 'O' to '9' and sent in BCD format. As stated above, the password should be suitable to change any time, i.e., while the initial password can be "0120", it can also be replaced by "3456" any time by the administrator. In this design, you are allowed to use only 4-bit parallel output shift-registers with a single-serial input data line and 4-bit magnitude comparators. The password to detect is "1234". Question - 2: Design a logic circuit to sum two different BCD numbers (A3A2A1A0) and (B3B2B1B0). The inputs MUST NOT be greater that 10. Assume that the logic circuit is driven by a clock with a period T and the mathematical operation should be performed at each 4×N T, where N is an integer. You should use 4-bit parallel output shift registers, full-adders, encoders, comparators, and 1-to-4 channel demultiplexer, and AND, NAND, and OR gates in your design.