(24 marks) Question 1: The specification of the Coffee Lake-based Core i7-9850H CPU is listed in the following table. Processor Name Cores L1-D Cache (per Core) L1-1 Cache (per Core) L2 Cache (per Core) L3 Cache Core i7-9850H 6 Capacity: 32 KB Organization: 8-way Set Associative Block Size: 64 Bytes Capacity: 32 KB Organization: 8-way Set Associative Block Size: 64 Bytes Capacity: 256 KB Organization: 4-way Set Associative Block Size: 64 Bytes Capacity: 12 MB Organization: 16-way Set Associative Block Size: 64 Bytes 2.6 GHz Base Clock Frequency Step Turbo Boost Parameters 100 MHz 15-15-17-18-19-20 (a) Determine the number of bits for the tag fields in the 38-bit memory address for: (i) L1-D Cache (ii) L2 Cache (4 marks) (4 marks) (b) (2 marks) (iii) Which cache eviction policy would you recommend for the L3 cache? Explain your answer. (i) L1 is splited into I Cache and D Cache. Give a reason to support such design. (ii) L3 is shared among cores rather separated and dedicated for each core. Give a reason to support such design. (2 marks) (2 marks) (iv) The cache block size is larger than the maximum data size operated on the processor. Explain whether this design would increase the hit rate or decrease the hit rate. (2 marks) (c) Determine (i) The generation number of this processor. (1 mark) (ii) The number of logical processors. (1 mark) (iii) The maximum core frequency when only half of the cores are active. (iv) The maximum core frequency when only 1 core is active. (3 marks) (3 marks)