Given the input probabilities, PA = PB = Pc = PD = 0.5. Inputs are uncorrelated. Please: 1) Find out the activity factor at the output of Fig. 5. 2) Estimate the dynamic power consumption. Given switching capacitance of 450 pF, and runs at 450 MHz at VDD=0.9 V. 3) Sketch a stick diagram of 2-input NAND gate, minimizing the contacts at the output. 4) Estimate the area of 2-input NAND gate from the stick diagram by using \ rules. A B D 0 U D Fig. 5: 4-Input NAND. I. FORMULA SHEET 1) NMOS: B = C(W/L), triode Ip = Bu((Vos-Vin)Vos-(VBs/2)); saturation fp = 1/2ẞ(VGS- V), subthreshold ID = IDoc((Ves Val(V) (1-e-Vus/V); Vth = V + (√√√SB+s - √s) 2) PMOS: BC (W/L), triode fp =B((VsG-Vin)VSD-(V/2)); saturation Ip = 1/28, (Vsc- |Ven)²; 3) Demorgan's Law: A 4) Noise margin: NM, B = = VIL A+ B; A+B A B VOL: NM VON - VIH 5) Delay model: d=gh+p; h = C - 6) Path delay: D = NF¹N + P; F = GHB; B is the branch effort; H is the path electrical effort; G is path logic effort; N = log 7) FO4 delay: 5 T 8) Elmore Delay: p≈ΣRi-to-source Ci 9) Power: Pdixx = αCVBD! 10) Activity factor: a = P-P 11) A metal wire track pitch is 8 12) Relative permittivity of SiO2: Cox = 3.9 13) Permittivity of free space: 8.854 10 12 F/m 14) Setup time: tschap Spey + d + skew 15) Hold time: hold Steeq +ted - takew L 16) R = Requare w 17) Cox - for 18) Pfailure = Ne-(Te-t-setup)/73 19) Output probabilities of various factor gates as a function of their input probabilities. Given inputs are uncorrelated. Gale AND2 Py PA-PB AND3 PA PB PC OR2 1-PA-PB NAND2 NOR2 XOK2 1-PA-PR PA PB PA PB+PA PB 20) Logical effort of static common gates Gate Type Number of Inputs 1 2 3 4 п INV NAND NOR 1 4/3 513 6/3 (n+2)/3 5/3 753 9/3 (2n+1)/3 21) Parasitic delay of static common gates Number of Inputs Gate Type 1 2 3 4 INV 1 NAND NOR 2 3 4 2 3 4 נו נו The common used Verilog HDL operators are listed in Table. III. TABLE III: Verilog Common Operators Operator Name Functional Group U bit select 0 parenthesis & reduction AND reduction reduction OR reduction -& reduction NAND reduction -| reduction NOR reduction reduction XOR reduction -or- reduction XNOR reduction [ ] concatenation concatenation 1 % « and » > and < 2 [{ }] multiply divide modulus replication replication arithmetic arithmetic arithmetic shift left/right shift greater less than relational >= and <= greater/less or equal relational === case equality equality case inequality equality & bit-wise AND hit-wise bit-wise XOR bit-wise I bit-wise OR bit-wise negation bit-wise && logical AND logical logical OR logical i logic negation logical 2: conditional conditional