Design a 4-to-1 multiplexer using multiple, as many as needed, 2-to-1 multiplexers following the steps below. 1- Define the entity of the 4-to-1 multiplexer where 10,11, 12, 13, SO,S1 are inputs and Mout represents the output. 2- Derive a VHDL code for a 2-to-1 multiplexor using a combinational process and a case statement. 3- Derive the block diagram of a 4-to-1 multiplexer using multiple 2-to1 multiplexers Make sure to annotate all inputs, outputs, signals and components 4- Derive the structural VHDL description for the 4-to-1 multiplexer (using 2-to-1 multiplexer as components). Fig Q Mout йос Si So O O Io IA HATE 4-10-1 MUX Fig a Mout In TJ TI 10005 Si So Io TE I 2 I 3 4-to-1 MUX TT S. So Mont