Problem 2: Cache Associativity For all the following cache design questions assume the following parameters: • 1 MIB RAM 32 kiB cache (doesn't include tag RAM) 64 byte cache lines How many address bits are required to address all bytes in RAM? Direct Mapped How many cache lines does the cache contain? Indicate for each field how many address bits are used for: ⚫the byte within the line the cache line index ⚫ the tag How many tags in cache do you compare the tag bits of the address with when checking if the address is in cache? cache RAM tay Indey kyle CPU addreve X 4-Way Set Associative How many cache lines does the cache contain? How many sets are in cache? How many lines per set are there? Indicate for each field how many address bits are used for: ⚫ the byte within the line the set index ⚫ the tag After indexing to a set, how many tags in cache do you compare the tag bits of the address with when checking if the address is in cache? CPU cache RA-M 00.0 address X Inday byte Fully Associative How many cache lines does the cache contain? Indicate for each field how many address bits are used for: ⚫ the byte within the line • . the index if any the tag How many tags in cache do you compare the tag bits of the address with when checking if the address is in cache? cache tes Рам ty Indy byte CPU address X