Consider the following circuit CLK- A-D Q B-D C-D Q tskew Assume that propagation delay is 15ps for the inverter, 20ps for the NAND gate, 30ps for the NOR gate and 60ps for the XOR gate. Also, assume that all the flip-flops are identical with too-35ps and tsu-30ps. c) [10 Pts] What is maximum clock frequency for reliable operation (tskew-0). d) [10 Pts] Assume that the circuit is modified so that the clock reaches X and Y before A, B and C (negative clock skew). What is the amount of negative clock skew the circuit can tolerate if it needs to operate at 5 Ghz.