Example: Performance of Multi-level Caches (cont.) Suppose we have a processor with a base CPI of 1.0, assuming all references hit in the primary cache, and a clock rate of 4 GHz. Assume a main memory access time of 100 ns, including all the miss handling. Suppose the miss rate per instruction at the primary cache is 2%. How much faster will the processor be if we add a secondary cache that has a 5 ns access time for either a hit or a miss and is large enough to reduce the miss rate to main memory to 0.5%? Solution: The miss penalty to main memory is 0.25 100 ns ns clock cycle = 400 clock cycles Example: Performance of Multi-level Caches (cont.) Suppose we have a processor with a base CPI of 1.0, assuming all references hit in the primary cache, and a clock rate of 4 GHz. Assume a main memory access time of 100 ns, including all the miss handling. Suppose the miss rate per instruction at the primary cache is 2%. How much faster will the processor be if we add a secondary cache that has a 5 ns access time for either a hit or a miss and is large enough to reduce the miss rate to main memory to 0.5%? Solution: The miss penalty to main memory is 0.25 100 ns ns clock cycle = 400 clock cycles Example: Performance of Multi-level Caches (cont.) • • Thus, for a two-level cache, total CPI is the sum of the stall cycles from both levels of cache and the base CPI: Total CPI = 1 +Primary stalls per instruction + Secondary stalls per instruction =1+2% x 20 +0.5% x 400 = 1 + 0.4 + 2.0 = 3.4 • Thus, the processor with the secondary cache is faster by 9.0/3.4= 2.6