3.2.6: Single Edge Controlled RS Flipflop Experiment.1: Fundamental Principles • Setting or resetting is only possible during the edge of the clock pulse When positive edge triggered clk: If S=0 → Set and if R=0 → Reset • Also, when clk is constant and =1 → a change on S or R switches the output S 1S Q1 ▷ C1 T 1R Fug.3 R D1 D3 a D5 Q1 Q2 b D6 D4 D2 Fig.4 Setup the previous circuit and complete the pulse diagram. T 0 1 S 0 1 R 1 Q1 0 Time Fig. 3.2.6.3 Pulse diagram of the single edge controlled RS flipflop t