Q2: The truth table below represents a FSM with a 1-bit input (IN) and a 2-bit output (OUT). A- Draw the state diagram? (3 Mark) B- How many bits you need for the state code? C- Is it Mealy or Moor model and why? (2 Mark) (2 Mark) D-Suppose the machine is initialized to its starting state B and then processes three input values: 1,0,0 (1 input bit after each Clk). What sequence of outputs does it produce and what is its final state? (Put one space in between each pair of outputs in your answer, ex: xx xx xx.)? E- Design the logic circuit of this FSM using T flip flop? IN S Next SOUT 0 AA 00 1 AB 11 0 BC 11 1 BD 00 0 CA 10 (3 Mark) 1 CB 01 (10 Mark) 0 DE 01 1 DD 10 0 EA 10 1 EB 01