For the Truth Table given below: (a) Construct a Karnaugh map for each F1 and F2. (b) Use the Karnaugh maps to determine the logic expressions for each F1 and F2, simplifying further using Boolean algebra where possible. (c) Sketch the simplified logic using standard logic symbols. A B C F1 F2 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 0 0 Using Boolean logic, simplify the following expression. Verify your answer using a Karnaugh map. = ABC + ADC + AC + ABD For the following logic diagram: (a) Determine the logic expression of the output, Q1, shown in the diagram. (b) Sketch the PLC ladder logic for the output, Q1, shown in the diagram. 11 12 13 14 Q1 The ladder logic below represents ZelloSoft code controlling digital outputs Q1 and Q2 T1 is a 2 second on delay (TON) timer. This is known in ZelloSoft as a Function A timer. Complete the timing diagram for the digital outputs Q1 and Q2. There is space allowed on the timing diagram for T1 If you need it. The vertical divisions on the timing chart represent 1 second. 11 11 1 TI 12 13 Q1 12 14 TT1 Q2 02 1