Q1: Given the following Combinational circuit, Use Verilog HDL on Quartus tool to Io 4 to 1 11 MUX 12 13 S1 So 2 to 1 MUX 4357 14 S₂ 16 4 to 1 MUX 17 S₁ So Output 1. Write a Verilog HDL code to describe the module mux4×1 // this module name must be your last name 2. Write a Verilog HDL code to describe the module mux2×1// this module name must be your first name 3. Write a Verilog HDL code to describe the whole system structurally from its subsystems // this module name must be your university number