3. Using an initial statement with a begin... end block write a Verilog description of the waveforms shown below. Repeat using a fork... join block. Enable A B C D E F 0 10 20 30 40 50 60 70 80 4. Draw the logic diagram for the sequential circuit described by the following Verilog HDL: module Seq_circuit (input A, B, C, CLK, output reg Q); reg E; always @(posedge CLK) begin E<= A || B; end endmodule Q <= E && C;