Q.1. It is required to design an iterative combinational circuit that computes the equation Z-3*X+Y, where X and Y are n-bit unsigned numbers. a) (5 points) Determine the number of inputs and outputs needed for your 1-bit cell. Explain the meaning of values in the interface signals. b) (8 points) Derive the truth table of your 1-bit cell. e) (12 points) Derive minimized equations for your 1-bit cell using K-Map method. d) (10 points) Write a Verilog module for modeling your 1-bit cell by using an assign statement for each output equation. e) (5 points) Write a Verilog module for modeling a 4-bit circuit based on the 1-bit module you have. f) (10 points) Write a Verilog test bench to test the correctness of your 4-bit module for the following input values: (X-2, Y-1), (X-2, Y-9), (X-3, Y-11), {X-15, Y-15). Allow a period of 20 ps between two consecutive test cases. g) (5 points) Submit a report (Word or PDF document) that should contain: i. Problem description ii. The 1-bit cell interface, 1-bit truth table and derived equations iii. A copy of the Verilog modules and test benches of parts (d) to (f) iv. The timing diagrams (waveforms) taken directly as snapshots from the simulator. Have as many snapshots as needed to cover all the test cases. b) iver Junch an Z= 3xn+y (a) Given X & Yore 1-bit element shinage. So X & Y are 1-bits ६५ Tot so inputs has 1-bit storage and output has 3-bit, Truth Table:- X4 22 220 00 000 0030+0=0 01 3x0+1=1 3x1+0=3 22X.4. (&) Verilog Code:- 010 3x1+1=4 Z₁ =xy Zo=xy + x y module (X, Y, 20, 2,2) =X@Y input XY; output Zo, 2, 22; assign 2₂ = X&4; assign Z₁ = XεNY. end alligan dub. 20 = x^y;