PROBLEM 4 (24 PTS) a) Complete the truth table describing the output of the following circuit and write the simplified Boolean equation (6 pts). x x y z 0 0 0 001 010 011 100 101 110 111 b) Complete the timing diagram of the logic circuit whose VHDL description is shown below: (5 pts) library leee; use ieee.std_logic_1164.all; entity circ is port (a, b, c: in std_logic; end circ; f: out std_logic); architecture struct of cire is signal x, y: std_logic; begin x<not (a) xor not (c); <y and (not b); y <- x nor b; end struct; c) The following is the timing diagram of a logic circuit with 3 inputs. Sketch the logic circuit that generates this waveform. Then, complete the VHDL code. (8 pts) library ieee; use ieee.std_logic_1164.all; entity wave is port (a, b, c: in std_logic; b f: out std_logic); end wave; architecture struct of wave is -222 begin f -222 end struct; d) Complete the timing diagram of the following circuit: (5 pts) U "