[20] Question 7: In Fig. 7, given the setup time and hold time of a DFF is 65 ps and 30 ps respectively. The clock-to-Q delay is 50 ps. And the clock cycle is 500 ps. Assume there is zero clock skew. 1) Determine the maximum logic propagation delay within one clock cycle. [4 marks] 2) Determine the maximum logic propagation delay if the clock skew between two DFFs can be up to 50 ps. [4 marks] 3) How to modify the circuit to avoid sampling the wrong value at the second DFF if the propagation delay is longer then 700 ps while still using the same clock? [4 marks] 4) Please draw a master-slave DFF in gate level (positive-edge trigger). [4 marks] 5) Please identify which devices determine setup and hold time (clearly label the devices). [4 marks] D IN D CLK D_OUT D COMB Fig. 7: Q7.